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UVM VIP for Pulp RISC-V uDMA
UVM
RISC-V
RTL
At ACCELR we have developed an open-source UVM verification environment for the PULP RISC-V platform. The An important sub-system of the PULP platform is the uDMA core. This uDMA core allows system designer's to plug in low speed peripherals such as UART, SPI and I2C peripheral IPs to the PULP CPUs. We have devised a UVM verification environment consisting of interfaces, agents and analysis components that will allow verification engineers to quickly build a verification environment for their low speed peripheral. Our initial release demonstrates this concept by way of a UART verification environment. We are currently working on extending this to support an SPI as well. Talk to our team for more information on our RISC-V and UVM experience
UVM VIP and verification environment
Fully customizable verification environment consisting of a full suit of agents, drivers and other verification components
Enables verification of uDMA peripherals prior to SoC integration
Allows RTL developers and verification engineers to fully validate their own uDMA compliant IP prior to integration to a PULP SoC
